The transition of the Radio Access Network (RAN) from a standalone, integrated network into a disaggregated, virtualized infrastructure is well underway. However, all open RAN deployments to date rely on Intel's x86-based COTS servers, with most deployments also using Intel's proprietary FlexRAN software architecture. Recently, various silicon vendors have announced that they are developing alternatives to Intel's x86 platform based on ASICs, GPUs as well RISC-V architectures. Several of these vendors are currently testing their new PCIe-based L1 accelerator card products with CSPs and commercial versions of these products are expected to become widely available during the next three years.
This report provides an overview of the emerging open RAN PCIe-based accelerator card market based on new merchant silicon and highlights the opportunities and technical challenges facing the open RAN chip community as they strive to develop alternative chip solutions capable of efficiently processing real-time, latency-sensitive Layer-1 workloads.
Table of Contetnts:
- Key Takeaways
- PCIe-based Hardware Acceleration
- Lookaside vs In-line Acceleration
- Technical Trade-offs
- Processor Architectures
- Types of Processors
- Comparison of Hardware Options
- Intel's Xeon with vRAN Boost
- Layer-1 Stack
- Reference of Commercial Grade Stack?
- Open or Closed Stacks?
- Layers 2 and 3
- Interoperability and Standardization
- FAPI Interface
- Proprietary L1 Software Stacks
- Accelerator Abstraction Layer (AAL)
- Saankya Labs RANwiser
- Key Players
- AMD Xilinx
- Leapfrog Semiconductor
Number of Pages: 18
Published Date: April 2023