LeapFrog Semiconductor develops RISC-V based AI-enhanced DSP for Wireless Infrastructure

Virtually all commercial open RAN deployments to date have used COTS server hardware based on Intel’s x86-based compute with or without FPGA hardware acceleration. While x86-based platforms are adequate for initial prototyping and low bandwidth deployments without acceleration, they are, however, expensive, power-hungry and highly inefficient for high-traffic, low-latency use cases requiring FPGA acceleration. Hence not the best choice for deployment at scale.

Open RAN’s Massive MIMO Challenge

Solving the massive MIMO performance deficit is one of the key issues inhibiting an industry wide transition to open RAN. This challenge must be resolved before mainstream adoption of massive MIMO radios can occur. However, this will require a new breed of merchant silicon solutions designed specifically to efficiently process real-time, latency-sensitive Layer-1 workloads such as beamforming, channel coding, etc.

In early 2023, a number of vendors demonstrated alternatives to Intel’s x86 platform at MWC in Barcelona based on ASICs, GPUs as well as RISC-V architectures. Late last year, an interesting new contender – LeapFrog Semiconductor – appeared on the market. 

LeapFrog’s RISC-V Based Modular, Customizable And First Truly Software Defined Layer-1 Solution

LeapFrog Semiconductor is an early-stage fabless semiconductor company focused solely on developing next-generation Layer-1 silicon and software solutions for the mobile infrastructure and enterprise markets. Founded in 2020, it is funded and staffed by seasoned semiconductor veterans.

The San Diego-based start-up has developed a unique AI-enhanced DSP-based silicon platform based on the RISC-V architecture as well as a Network-on-Chip silicon design. The  result is a multi-core, distributed 5G RAN silicon platform, which is modular, customizable and flexible, thus creating the first truly software defined, AI-enhanced RAN solution.

LeapFrog’s DSP Chip

Known as the LeapFrog Processing Unit (LPU), LeapFrog’s DSP core uses a specialized Instruction Set Architecture (ISA) developed in-house that natively supports fine-grain parallelism. This means that Layer-1 computation is broken down into a large number of small tasks, resulting in a high level of parallelism. Together with its programmable NOC architecture which minimises communication and synchronization overheads, LeapFrog’s Layer-1 chip results in several unique benefits:

  • Power and area efficient design – LeapFrog claims that its SoC is significantly smaller than rival designs and boasts single-digit (<10W) power consumption.
  • Software-based Layer-1 solutions – LeapFrog’s RU and DU Layer-1 solutions are 100% software-based and are thus fully programmable, with no requirements for hardware-based accelerators.
  • AI-enhanced L1 chip solution – the LeapFrog chip includes in-line processing of AI and L1 algorithms, which includes AI-based channel estimation and other L1 algorithms. This results in a low-latency chip solution and hence improved RAN system performance.
  • Tile and chiplet-based silicon design – resulting in a scalable, customizable and modular design which can be optimized for different deployment scenarios. For example, chiplets can be combined to make different functions such as L1, I/O, CPU, etc.

In contrast, many rival open RAN chip designs currently under development are based on coarse-grained parallelism, thus necessitating the use of hardware accelerators or hard IP blocks. These designs are not as scalable as LeapFrog’s solution and offer very little flexibility with respect to changes in the computation logic. As a result, a new chip tape-out would be needed if any architectural or logic changes are required.

LeapFrog Network-on-Chip (LNOC)

LeapFrog has also developed a highly power efficient, programmable LeapFrog Network-on-Chip (LNOC) chip design which connects multiple LPUs to create a multi-core, distributed 5G RAN silicon platform. Leveraging innovations in chiplet and Die2Die (D2D) technologies, this results in a highly scalable, modular and flexible chip design complying with all 5G O-RAN specifications (Exhibit 1).

©Leapfrog Semiconductor

Exhibit 1: LeapFrog Semiconductor’s RISC-V 5G Layer 1 Silicon Architecture

LeapFrog believes that its LNOC design is currently the only chiplet-based 5G open RAN chip platform with a fully software-based RU and DU L1 solution that can be easily customized to suit different 5G deployment scenarios.  In addition, the company claims that its AI-enhanced L1 solution results in 50% to 100% better system performance and 10x lower cost and power compared to existing open RAN RU and DU platforms. Another benefit is that software development and testing can be performed on an FPGA platform, which is then transferred to LeapFrog’s silicon platform. This allows a faster time-to-market compared to alternative designs from other vendors. 

Target Markets

LeapFrog is targeting multiple markets with its unique LPU design. Chiplet based productization allows the same platform to scale all the way from small cell, fixed wireless access (FWA) to macro cell RU and DU market with a major focus on massive MIMO networks. Potential customers include small and large 5G infrastructure vendors, greenfield CSPs as well as hyperscalers. The company is also pursuing an IP licensing model for its general-purpose DSP targeting consumer/industrial IoT modems, wireless CPEs/gateways, automotive connectivity/sensor fusion as well as mobile handset modems. The IP is ready on FPGA now and was recently demonstrated at the India Mobile Congress and the RISC-V Summit in 2023. The chip design was tested in H2 2023 and delivery of samples to customers is expected to start in Q2 2024.

Related Posts

Gareth has been a technology analyst for over 20 years and has compiled research reports and market share/forecast studies on a range of topics, including wireless technologies, AI & computing, automotive, smartphone hardware, sensors and semiconductors, digital broadcasting and satellite communications.

Term of Use and Privacy Policy

Counterpoint Technology Market Research Limited


In order to access Counterpoint Technology Market Research Limited (Company or We hereafter) Web sites, you may be asked to complete a registration form. You are required to provide contact information which is used to enhance the user experience and determine whether you are a paid subscriber or not.
Personal Information When you register on we ask you for personal information. We use this information to provide you with the best advice and highest-quality service as well as with offers that we think are relevant to you. We may also contact you regarding a Web site problem or other customer service-related issues. We do not sell, share or rent personal information about you collected on Company Web sites.

How to unsubscribe and Termination

You may request to terminate your account or unsubscribe to any email subscriptions or mailing lists at any time. In accessing and using this Website, User agrees to comply with all applicable laws and agrees not to take any action that would compromise the security or viability of this Website. The Company may terminate User’s access to this Website at any time for any reason. The terms hereunder regarding Accuracy of Information and Third Party Rights shall survive termination.

Website Content and Copyright

This Website is the property of Counterpoint and is protected by international copyright law and conventions. We grant users the right to access and use the Website, so long as such use is for internal information purposes, and User does not alter, copy, disseminate, redistribute or republish any content or feature of this Website. User acknowledges that access to and use of this Website is subject to these TERMS OF USE and any expanded access or use must be approved in writing by the Company.
– Passwords are for user’s individual use
– Passwords may not be shared with others
– Users may not store documents in shared folders.
– Users may not redistribute documents to non-users unless otherwise stated in their contract terms.

Changes or Updates to the Website

The Company reserves the right to change, update or discontinue any aspect of this Website at any time without notice. Your continued use of the Website after any such change constitutes your agreement to these TERMS OF USE, as modified.
Accuracy of Information: While the information contained on this Website has been obtained from sources believed to be reliable, We disclaims all warranties as to the accuracy, completeness or adequacy of such information. User assumes sole responsibility for the use it makes of this Website to achieve his/her intended results.

Third Party Links: This Website may contain links to other third party websites, which are provided as additional resources for the convenience of Users. We do not endorse, sponsor or accept any responsibility for these third party websites, User agrees to direct any concerns relating to these third party websites to the relevant website administrator.

Cookies and Tracking

We may monitor how you use our Web sites. It is used solely for purposes of enabling us to provide you with a personalized Web site experience.
This data may also be used in the aggregate, to identify appropriate product offerings and subscription plans.
Cookies may be set in order to identify you and determine your access privileges. Cookies are simply identifiers. You have the ability to delete cookie files from your hard disk drive.