The transition of the Radio Access Network (RAN) from a standalone, integrated network into a disaggregated, virtualized solution is well underway. However, all open RAN deployments to date rely on Intel’s x86-based COTS servers, with most deployments also using Intel’s proprietary FlexRAN software architecture. Recently, various silicon vendors have announced that they are developing alternatives to Intel’s x86 platform based on ASICs, GPUs as well RISC-V architectures. Several of these vendors are currently testing their new PCIe-based Layer-1 accelerator cards with CSPs and commercial versions of these products are expected to become widely available during the next three years.
This report provides an overview of the emerging open RAN PCIe-based Layer-1 accelerator card market based on new merchant silicon and highlights the opportunities and technical challenges facing the open RAN chip community as they strive to develop alternative chip solutions capable of efficiently processing real-time, latency-sensitive Layer-1 workloads.
Key Takeaway No. 1: Too much diversity?
The launch of new L1 accelerator cards from various vendors, large and small, should be welcomed by CSPs calling for diversity and will go some way to quell criticism that the open RAN market is too Intel-based. However, CSPs may now be faced with another dilemma – too much choice! They must now face the difficult challenge of testing and comparing multiple accelerator cards, inevitably involving complicated technical and commercial trade-offs.
Key Takeaway No. 2: Look-Aside or In-Line Accelerators?
At present, the choice of accelerator architecture is binary: either look-aside or inline. Both types have their advantages and drawbacks. Depending on use cases and applications, Counterpoint Research believes that operators may need to use both types of accelerators. However, only one vendor currently offers a software/silicon platform with the capability to do this.
Key Takeaway No. 3: Interoperability and Vendor Lock-In
Developing commercial-grade Layer 1 software suitable for massive MIMO networks is an expensive process requiring very specific skills and a lot of experience – but with no guarantee of commercial success. Although open RAN is designed to promote interoperability and vendor diversity, all L1 stacks are currently tied to the underlying silicon architectures and hence are not portable between hardware platforms. This introduces a new form of vendor lock-in for CSPs. Clearly, there is an urgent need for an universal software abstraction layer between the L1 stack and the various hardware platforms to enable stack portability.
The complete versions of these Key Takeaways, including the full set of Takeaways is published in the following report, available to clients of Counterpoint Research’s 5G Network Infrastructure (5GNI) Service.
Table of Contents
- Key Takeaways
- PCIe-based Hardware Acceleration
- Look Aside vs In-Line Acceleration
- Technical Trade-Offs
- Processor Architectures
- Types of Processors
- Comparison of Hardware Options
- Intel’s Xeon with vRAN Boost
- Layer-1 Stacks
- Reference or Commercial Grade Stacks?
- Open or Closed Stacks?
- Layers 2 and 3
- Interoperability and Standardization
- FAPI Interface
- Proprietary L1 Software Stacks
- Accelerator Abstraction Layer (AAL)
- Saankya Labs RANwiser
- Key Players (in alphabetical order)
- AMD Xilinx
- Leapfrog Semiconductor