New Layer-1 Accelerator Cards Set To Boost Open RAN Market – Or Create More Lock-In?

The transition of the Radio Access Network (RAN) from a standalone, integrated network into a disaggregated, virtualized solution is well underway. However, all open RAN deployments to date rely on Intel’s x86-based COTS servers, with most deployments also using Intel’s proprietary FlexRAN software architecture. Recently, various silicon vendors have announced that they are developing alternatives to Intel’s x86 platform based on ASICs, GPUs as well RISC-V architectures. Several of these vendors are currently testing their new PCIe-based Layer-1 accelerator cards with CSPs and commercial versions of these products are expected to become widely available during the next three years.

This report provides an overview of the emerging open RAN PCIe-based Layer-1 accelerator card market based on new merchant silicon and highlights the opportunities and technical challenges facing the open RAN chip community as they strive to develop alternative chip solutions capable of efficiently processing real-time, latency-sensitive Layer-1 workloads.

Key Takeaway No. 1: Too much diversity?

The launch of new L1 accelerator cards from various vendors, large and small, should be welcomed by CSPs calling for diversity and will go some way to quell criticism that the open RAN market is too Intel-based. However, CSPs may now be faced with another dilemma – too much choice! They must now face the difficult challenge of testing and comparing multiple accelerator cards, inevitably involving complicated technical and commercial trade-offs.

Key Takeaway No. 2: Look-Aside or In-Line Accelerators?

At present, the choice of accelerator architecture is binary: either look-aside or inline. Both types have their advantages and drawbacks. Depending on use cases and applications, Counterpoint Research believes that operators may need to use both types of accelerators. However, only one vendor currently offers a software/silicon platform with the capability to do this.

Key Takeaway No. 3: Interoperability and Vendor Lock-In

Developing commercial-grade Layer 1 software suitable for massive MIMO networks is an expensive process requiring very specific skills and a lot of experience – but with no guarantee of commercial success. Although open RAN is designed to promote interoperability and vendor diversity, all L1 stacks are currently tied to the underlying silicon architectures and hence are not portable between hardware platforms. This introduces a new form of vendor lock-in for CSPs. Clearly, there is an urgent need for an universal software abstraction layer between the L1 stack and the various hardware platforms to enable stack portability.

The complete versions of these Key Takeaways, including the full set of  Takeaways is published in the following report, available to clients of Counterpoint Research’s 5G Network Infrastructure (5GNI) Service.

Report: New L1 Accelerator Cards Set To Boost Open RAN Market – Or Create More Lock-In?

Table of Contents

  • Snapshot
  • Key Takeaways
  • Introduction
  • PCIe-based Hardware Acceleration
    • Look Aside vs In-Line Acceleration
    • Technical Trade-Offs
  • Processor Architectures
    • Types of Processors
    • Comparison of Hardware Options
    • Intel’s Xeon with vRAN Boost
  • Layer-1 Stacks
    • Reference or Commercial Grade Stacks?
    • Open or Closed Stacks?
    • Layers 2 and 3

  • Interoperability and Standardization
    • FAPI Interface
    • Proprietary L1 Software Stacks
    • Accelerator Abstraction Layer (AAL)
    • Saankya Labs RANwiser
  • Key Players (in alphabetical order)
    • AMD Xilinx
    • Dell
    • EdgeQ
    • Intel
    • Leapfrog Semiconductor
    • Marvell
    • Nvidia
    • Picocom
    • Qualcomm
  • Viewpoint

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Chip Vendors Showcase Open RAN Merchant Silicon Solutions at MWC-22

All open RAN deployments to date have used COTS server hardware based on Intel’s FlexRAN architecture with or without hardware acceleration. While x86-based compute may be adequate for rural deployments with low processing requirements, it is not sufficient for urban, high-traffic deployments using mMIMO radios.

Intel’s FlexRAN architecture typically only offloads a small subset of a base station’s L1 functions – such as forward error correction – from the host processor to an external FPGA-based “look aside” accelerator.  A high number of CPU cores are therefore required to support 5G Layer 1 and other data-centric processing tasks leading to high power consumption. Latency is also an issue.

As a result, the FlexRAN architecture cannot compete with the proprietary, integrated solutions available today from the incumbent vendors. Last year, a number of vendors announced that they were developing alternative merchant chip solutions based on ASICs, GPUs and even RISC-V architectures. Several of these vendors showcased their new designs at MWC this week.

Qualcomm’s X100 Accelerator

Qualcomm is showing its X100 5G RAN accelerator card and has announced a slew of partnerships. In contrast to Intel’s FlexRAN, the X100 in an “in-line” DSP-based PCIe accelerator card that offloads all latency-sensitive L1 processing, thus reducing the number of CPU cores required.

The X100 card will initially be offered in HPE’s ProLiant DL110 Gen10 Plus carrier-grade server. Qualcomm also announced a partnership with Rakuten, whereby the X100 will be used in Rakuten’s 64T/64R mMIMO radio units and DU units, to be deployed first in Rakuten’s network in Japan and then offered as part of Rakuten’s Symphony Symware portfolio. In addition, Qualcomm announced a partnership with Mavenir, where the X100 technology will be used in its 2nd generation mMIMO radios – possibly replacing Xilinx’s FPGAs? In Japan, Qualcomm already has partnerships with NTT DoCoMo and compatriot NEC, with the X100 being used in NEC’s DU unit, presumably using HPE’s servers.

Sampling of the X100 card is planned for mid-2022 with general availability expected in Q2 2023. Commercial products are expected to become available at the end of 2023.

Marvell’s Octeon-based Solutions

Marvell is showcasing its open RAN mMIMO RU and DU reference designs based on its Octeon Fusion processor, which integrates 5G in-line acceleration and ARM Neoverse CPUs. The Octeon processor is already widely deployed in traditional, integrated base stations and supports 5G DU processing with full O-RAN compliance. Marvell’s platform incorporates a range of 5G L1 hardware accelerators that offload all L1 processing from the host server to a Marvell Network Interface Card (NIC). Interestingly, the vendor’s Octeon processors can be customized and integrated with individual customers’ proprietary IP. Marvell claims that its designs result in a 15x reduction in power per base station compared to Intel’s FlexRAN.

Marvell has partnered with Dell and its Octeon-based open RAN DU solutions will be used in the server vendor’s PowerEdge and other x86-based servers. Solutions are set for global availability in late 2022.

Xilinx and Nvidia

Like Intel, Xilinx is in the FPGA camp and the vendor is demonstrating an open RAN 64T/64R mMIMO prototype running on a Keysight Technologies DU emulator. Xilinx launched a telco accelerator card some time ago and has an open RAN 5G vRAN demo at MWC complete with its telco accelerator card plus DU/CU units running on an AMD server. Nvidia announced its AI-on-5G platform last year and is working with Mavenir, Radisys and Wind River.

RISC-V Designs

Open-source based RISC-V may be an alternative architecture to x86 and ARM-based designs. Two companies developing open RAN RISC-V-based chips are EdgeQ and Picocom. EdgeQ is currently sampling its first products while small-cell chip vendor Picocom announced its first design win with Blinq Networks.


It is becoming clear that a disruptive open RAN ecosystem needs merchant silicon solutions if it is to be able to compete against the proprietary RAN products optimised for performance, power and cost from the likes of Huawei, Ericsson and Nokia.

Although still early days, the open RAN merchant silicon market may already be developing into a two-horse race: with Qualcomm challenging industry leader Marvell. At this time, FPGA and GPU-based alternatives from Xilinx and Nvidia respectively seem to playing second fiddle, at least in terms of announcements.

Challenger Qualcomm has ambitions to become a major player in the macro base station market. A dominant small-cell chip vendor, it sees open RAN as an entry point into the main market. Unsurprisingly, Qualcomm is engaging mostly with emerging open RAN stalwarts such as Mavenir, Rakuten and vendor NEC, who itself sees open RAN as a key differentiator to increase its RAN market share globally.

Meanwhile Marvell is the undisputed leader in base station baseband processing supplying all the major mobile infrastructure vendors, with the exception of Huawei. With its Octeon processor it will be able to supply both proprietary vRAN and O-RAN applications using essentially the same processor design. At present, it looks as if it is 12 months ahead of Qualcomm in terms of product availability. Marvell claims it already has five design wins under its belt, including at least one incumbent vendor – probably Nokia or Samsung – and possibly one or two webscale clients.



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